The invention relates to distribution of signals in an electronic device. More particularly, the invention relates to distribution and synchronization of clock signals.
Typical clock distribution schemes consist of a clock generation circuit that provides a clock signal to one or more components. If a large number of components receive the clock signal, buffers can be used to boost the clock signal before the clock signal is distributed to the components in order to avoid fan out problems.
FIG. 1 is a block diagram of a prior art clock distribution scheme. System 100 includes clock generation circuit 110 that generates one or more clock signals. The clock signals are distributed to buffers 120, 124 and 128 for signal boosting and distribution to components 130, 132, 134, 136, 138, 140, 142, 144 and 146.
System 100 effectively distributes the clock signal(s) generated by clock generation circuit 110. However, each device of system 100 requires space on a printed circuit board and wires for interconnections between the devices. Therefore, the more devices that are included within system 100, the more complicated and expensive system 100 becomes.
What is needed is a clock signal distribution scheme that includes fewer devices in order to simplify an electronic system in which the clock signals are distributed.
Methods and apparatuses for clock signal distribution and synchronization are described. In one embodiment, a system includes a system clock generation circuit to generate a system clock signal. A plurality of clock generation circuits are coupled to receive the system clock signal. The clock generation circuits generate component clock signals based on the system clock signal. A buffer is coupled between the system clock generation circuit and the clock generation circuits. The buffer passes the clock signal to the clock generation circuits for a first predetermined period of time and, at the expiration of the first predetermined period of time, the buffer blocks the system clock from the clock generation circuits for a second predetermined period of time. The buffer passes the system clock signal to the clock generation circuits at the expiration of the second predetermined period of time. The clock generation circuits synchronize to the system clock during the first predetermined period of time and again after the expiration of the second predetermined period of time and the component clock signals have a common phase after the expiration of the second predetermined period of time.